Serial Peripheral Interface (SPI)

The Serial Peripheral Interface (SPI) is a four-wire, single-master, synchronous serial communication bus. Common uses are for sensor communication in embedded systems [1].

The SPI bus has 4 logic signals. They are:

  • SCLK : Serial Clock (output from master).
  • MOSI : Master Output, Slave Input (output from master).
  • MISO : Master Input, Slave Output (output from slave).
  • SS : Slave Select (active low, output from master).

Independent slave configuration

The normal mode of operation of SPI devices is in an independent slave configuration. In this configuration, all MOSI pins are tied together and the all MISO pins are tied together while each slave has an independent slave select connection to the master as shown in Figure 1. There is also a Daisy chained configuration [1].

Figure 1: SPI devices in an independent slave configuration. Used with permission.

Clock timing modes

Figure 2: SPI clock timing diagram. Used with Permission

SPI devices have 4 modes of operation. They control the clock polarity (CPOL) and the clock phase (CPHA) as shown in Figure 2. The clock polarity basically controls whether the clock idles on a high signal or a low signal. The clock phase controls whether a bit is read on the clock signal's rising edge or falling edge[2].

The 4 modes are:

Table 1: The 4 SPI modes.


[1], accessed on April 1st, 2014.
[2], accessed on April 1st, 2014.

Documentation License: