DIY Surfmaster Pi Metal Detector

Warning: This documentation is in development. The development is being completed in an open fashion to attract interested parties. The information provided should not be assumed to be correct as it is in a state of constant flux. This is an exercise in technical documentation. Is anybody out there? Leave a message.

Figure 1: The schematic for the Surfmaster PI. Downloaded from


This project is based on the Whites original Surfmaster PI. It does not appear as though White Metal Detectors is still selling their Surfmaster PI, however they do sell a newer model called the Surfmaster PI Dual Field.

The Surfmaster PI circuitry schematic is publicly available. Though Whites no longer sells it, a kit is available from Silverdog in the UK. There's also a good build guide for the Silverdog Surf PI 1.2 kit at

What this page will aim to do is describe in detail how the original Surfmaster PI circuit works. With an understanding of how the circuit works, modifications can be made to improve it.

Circuit analysis

The power supply block

Figure 2: The power circuit block.

The power circuit block takes the steady 12V from a battery power supply, switch interruptible. It also provide +5V power from the output of the LM7805. This 5V is supplied to an ICL7660 IC. The latter is a CMOS power supply device that takes a +5V logic supply and provides +/- 5V power rails.

The PWM block

Figure 3: The PWM circuit block.

At the heart of the circuit is a simple 555 timer set to produce a PWM signal at a frequency of 615Hz and a duty cycle of 96%. The values for R1, R2 and C1, control the 555. The output of the 555 timer, pin 3, is driven through R3 to the base of Q1, a 2N3906 PNP transistor. When the 555 timer pin is high, Q1's base voltage is 12V, and no current passes from emitter to base; the transistor is in open circuit (no current from emitter to collector) 96% of the time. When Q1 acts as an open circuit switch, the voltage delivered to the base of Q2 is also at 12V, similarly preventing current flow.

The Q2 transistor, has its base pin at 12V 96% of the time but sees the voltage drop to 3.5V the other 4% of the time because of voltage divider resistors R4 and R5 between +12V and -5V power supply rails. When the base of Q2 is 3.5V, it allows current to flow from collector to base and switches on the transistor, driving large currents through the coil block. The timer block serves two other purposes: something something ICL7660, and to drive the time delayed logic block.

The coil block

Figure 4: The coil block

Charging up the coil

The TIP32C PNP transistor, Q2, is closed. No current is flowing through the coil. Pin3 is 0V. The output of the negative feedback configuration op amp U2 (low distortion NE5534 op amp), pin 6, and the output of the coil block, is therefore also 0V.

The Q2 transitor is switched on and allows full current through for a duration of 6.5e-5s, 615 times a second. When this happens the first pin of the coil, effectively has a full 12V applied while the other pin is grounded. A coil, initially with no current flowing through will resist the change in current. If the coil has an inductance of 350uH, with 12V across the inductor, the current passing through it will rise from 0A at a rate of 3.43e4A/s. At the end of 6.5e-5s, the current flowing through the inductor will have reached 2.24A by the time Q2 is instantly turned off.

Because a coil resists a change in current, the coil will continue to drive the 2.24A through the remainder of the circuit. At first glance it appears that the coil sees no downstream resistance and drives the 2.24A current straight to ground, however that current must originate from somewhere. It is actually sucking up its own current through R6, and R7/D1. At first, The current flowing through R6 and R7 are 1.84A and 0.4A respectively; generating voltages across their resistors of 404V and 89V respectively. The op amp's pin 3 however is 400V which saturates pin 6 to +5V. While this is happening, the current flow will drop at a rate of 0A/s, resisted by the R6/R7. Practically speaking, because the op amp is in such a high gain configuration, only when its voltage at pin 3 reach 0V will the voltage at pin 3 change for +5V to 0V.

The logic block


Figure 5: The PWM block.

At the heart of the logic block is a MCJ14093B chip that holds 4 NAND logic gates with fast switching Schottky triggers. The inputs of the NAND gates will be read as on when the pin voltage swings higher than 0.9V and will read as off when the voltage swings down below -1.1V. The output pin is always HIGH unless both input pins are registered as on, the only time the output pin is LOW.

Pin 9 on on the U4/C (from the MCJ14093B chip), which is one of the input pin to the first NAND gate, is connected to +V which reads as HIGH. The other input pin, pin 8, is pulled HIGH to the +V supply rail, through a 50K trim pot followed by a 100k case mounted pot. The pots in series can supply a resistance range from 0Ohms to 150kOhms. The rest of this discussion assumes the trim pot is shorted to 0Ohm.

96% of the time, the signal from the PWM block is pulled down to -V through R5, a 100ohm resistor. When the transistor Q1 is switched off, the steady state voltage across the C9 capacitor should be 10V (+V minus -V), given enough time to build the charge. With both pins HIGH, the gate's output signal is LOW. Following the logic through the NAND gate cascade, the other NAND gates are found to also be outputting LOW signals too since they are all in an almost identical configuration. When the Q1 transistor is switched on for 4% of the cycle. Because of the voltage divider created by R4 and R5, the voltage of the connection from the PWM block changes to half way between +12V and -5V, which is 3.5V, give the steady state voltage across the C9 capacitor is 1.5V.

The behaviour of U4/C

As soon as Q1 is switched on, C9 may not have had a chance to build up a full charge of +10V or to fully discharge when Q1 is switched off. The actual charge in C9 as soon as Q1 is switched on/off is dependent on the resistance of R25 and the 100K pot. The following discussion assumes that R25 is set to 30% of its 50K resistance. This is the same resistance used by Silverdog's SurfPI 1.4 to replace the R25 trim pot.

If the 100K pot provides no resistance, the time constant of the U4/C high pass filter quite fast: 1.5e-5s. The charge in the C9 would have reached 9.74V. When Q1 switch on, the voltage at pin 8 of U4/C instantly rises to 14.74V and C9 starts discharging. By the time Q1 switches off, the voltage charge in C9 drops to 0.13V, and so the voltage at pin 8 instantly drops to -4.87V, when C9 starts charging. This is illustrated in Figure 6.

Figure 6: A plot of the timing of the input and output signals passing through the U4/C NAND gate as a percent of the cycle.

Effectively, the resistor-capacitor pair R25 and C9 form a high-pass filter. The time constant for the capacitor's charge time in this configuration is $\tau = RC = 5.0e-5s$. The 4% duration pulse from the PWM block lasts 6.5e-5s. The voltage change across the capacitor in an RC high-pass filter can be calculated using the following exponential function:

$$V(t) = V_o(1-e^{-\frac{t}{\tau}})$$

while charging, or:

$$V(t) = V_oe^{-\frac{t}{\tau}}$$

while discharging, where $V(t)$ is the capacitor's charge voltage after $t$ seconds has elapsed, $V_o$ is the initial capacitor charge voltage, and $\tau$ is the RC time constant given by multiplying the resistance times the capacitance of the pair [1].

Because of the voltage differential between the +V rail, and the 3.5V from the PWM pulse signal, the capacitor charged is drained through the resistor R25 down to a voltage of +7.3V for a total capacitor charge of 2.3V. When the PWM block connection is pulled down to -5V again, capacitor C9, which now has a charge of 2.3V, has its NAND gate pin instantly pulled down to -2.7V. The charge in the capacitor is built up over time again through the R25 pull-up resistor. The voltage in the capacitor will take 4.5% of the cycle time to reach 0.9V and trigger a HIGH signal on the input of U4/C as shown in Figure 6. Therefore, U4/C's output signal goes HIGH starting when the PWM signal goes LOW at a time of 4% cycle, and stays HIGH until a time of 8.5% cycle.

U4/A has a 51k resistor, R26, coupled by a 0.001uF capacitor, C10, creating a high pass filter time constant of 5.1e-5s. When the output signal from U4/C (pin 10) is LOW, the other C10 capacitor's pin is pull HIGH for a total capacitor charge of +10V as shown in Figure 7. When the output signal from U4/C goes HIGH, it pushes the input voltage to U4/A's pin 6 instantly to +15V, which over the course of U4/C's output signal's pulse duration of 4.5% cycle duration, will drop to 7.4V.

Figure 7: A plot of the timing of the input and output signals passing through the U4/A NAND gate as a percent of the cycle.

When U4/C's output drops to LOW and pulls U4/A's input instantly down to 2.4V, it triggers U4/A's input to LOW and triggers it's output to go HIGH. U4/A's input pin voltage stays below 0.9V for a duration of 4.7%, ending its output pulse at a cycle time of 13.2%.

Figure 7: A plot of the timing of the input and output signals passing through the U4/D NAND gate as a percent of the cycle.

Figure 9: A plot of the timing of the input and output signals passing through the U4/B NAND gate as a percent of the cycle.

[1], May 05, 23.



Hi sir
would you please tel me how can make a signal like the red one (The behaviour of U4/C) to have a double polarity signal???
thanks a lot...

Brilliant; thanks for the great analysis.

There seem to be quiet a few Surf PI 1.2 builders / articles hinting that, providing your willing to dig everything, that the delay / discrimination should effectively run at it's fastest setting. The funny thing is the most complex portion of this circuit, 'the logic block', appears to have been designed to provide that sole discrimination feature.

Hello There,
Awesome surf break down tutorial. where are the rest of the blocks?

Thanks, Nate

I believe the last fellow is asking how the 7660, appears to have an asymmetric output with negative peak limiting.
I think what i'm seeing is a diode pump actually meeting the regulated +5 v. on the positive peaks?

Hi folks,

Thanks for the comments. Unfortunately this tutorial is incomplete. My interests are often shifting, I will likely continue this work at a later time. Right now my attention is on other projects :(.

You guys think there's enough interest here for a viable product?

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